1. Field of the Invention
The present invention relates to the field of CMOS analog circuits and CMOS analog circuit design.
2. Prior Art
The design of analog circuits in state of the art CMOS process technology involves the use of minimum channel length devices. The benefits of minimum channel length devices are increased device speed (i.e. ft) and reduced bulk parasitics. The drawbacks of a minimum channel length device include increased 1/f noise and channel length modulation, among others. Ideally when a MOS device operates in saturation, the drain current would be independent of the drain-source voltage, thereby having an infinite output resistance. In fact, however, channel length modulation causes an increase in the drain current with drain voltage for a constant gate-source voltage when operating in the saturation region, much like the Early effect in bipolar junction transistors. (See for instance Figure 2.42 on page 110 of “Bipolar and MOS Analog Integrated Circuit Design” by Alan B. Grebene.) Thus channel length modulation causes a decrease in the effective output resistance of a device and can have derogatory effects on the linearity of a basic source follower circuit.